Design and demonstration of micro-electro-mechanical relay multipliers

This paper describes the micro-architecture and circuit techniques for building multipliers with micro-electromechanical (MEM) relays. By optimizing the circuits and micro-architecture to suit relay device characteristics, the performance of the relay based multiplier is improved by a factor of ∼8× over any known static CMOS-style implementation, and ∼4× over CMOS pass-gate equivalent implementations. A 16-bit relay multiplier is shown to offer ∼10× lower energy per operation at sub-10 MOPS throughputs when compared to an optimized CMOS multiplier at an equivalent 90 nm technology node. To demonstrate the viability of this technology, we experimentally demonstrate the operation of the primary multiplier building block: a full (7:3) compressor, built with 98 MEM-relays, which is the largest working MEM-relay circuit reported to date.

[1]  O. L. Macsorley.  High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.

[2]  G. De Micheli,et al.  Circuit and architecture trade-offs for high-speed multiplication , 1991 .

[3]  Tsu-Jae King Liu,et al.  Design and reliability of a micro-relay technology for zero-standby-power digital logic applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[4]  S. Hsu,et al.  A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS , 2005, IEEE Journal of Solid-State Circuits.

[5]  Vladimir Stojanovic,et al.  Integrated circuit design with NEM relays , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[6]  Tack-Don Han,et al.  Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[7]  Tsu-Jae King Liu,et al.  Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic , 2011, IEEE Transactions on Electron Devices.

[8]  Elad Alon,et al.  Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications , 2011, IEEE Journal of Solid-State Circuits.