Comparison of 6T-SRAM cell designs using DTMOS and VTMOS for low power applications

SRAM (Static Random Access Memory) is a type of semiconductor memory that is designed to replace DRAMs for reducing power consumption and act as a CPU interface. It plays an important role for cache memory therefore its power dissipation reduction is the main concern. This paper compare three 6T-SRAM cell designs which are conventional; sleep and stack by using two body bias techniques that is DTMOS and VTMOS. Simulation are done using SPICE for 180nm technology parameter and simulated at 0.35V supply voltage. The comparative study of techniques shows that power of VTMOS is less whereas delay of DTMOS is low. Furthermore; sleep 6T-SRAM cell design shows minimum power consumption.