Comparison of 6T-SRAM cell designs using DTMOS and VTMOS for low power applications
暂无分享,去创建一个
[1] M. Satyam,et al. Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Universal Logic Gates , 2010, VLSIC 2010.
[2] Dhiraj K. Pradhan,et al. A single ended 6T SRAM cell design for ultra-low-voltage applications , 2008, IEICE Electron. Express.
[3] W. Dehaene,et al. Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.
[4] Kaushik Roy,et al. A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[5] Andreas Moshovos,et al. Low-leakage asymmetric-cell SRAM , 2002, ISLPED '02.
[6] Manoj Sachdev,et al. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test , 2008 .
[7] Hiroyuki Yamauchi. A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[8] Andreas Moshovos,et al. Low-leakage asymmetric-cell SRAM , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[9] Kaushik Roy,et al. A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.