Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops

Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than -22 dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18 μm digital CMOS process, the prototype PLL occupies an area of 0.18 μm and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively.

[1]  E. Alon,et al.  Replica compensated linear regulators for supply-regulated phase-locked loops , 2006, IEEE Journal of Solid-State Circuits.

[2]  Georges G. E. Gielen,et al.  Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  M. Horowitz,et al.  Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[4]  J. Choma,et al.  A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter , 2001, IEEE J. Solid State Circuits.

[5]  C. Piguet,et al.  A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[6]  Jaeha Kim,et al.  Variable domain transformation for linear PAC analysis of mixed-signal systems , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[7]  Pavan Kumar Hanumolu,et al.  Analysis of charge-pump phase-locked loops , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  S. Gondi,et al.  Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture , 2009, IEEE Journal of Solid-State Circuits.

[9]  Kjell Jeppson,et al.  Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay , 1994 .

[10]  Chien-Nan Jimmy Liu,et al.  Fast and Accurate Analysis of Supply Noise Effects in PLL With Noise Interactions , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  R. Castello,et al.  A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications , 2004, IEEE Journal of Solid-State Circuits.

[12]  Alper Demir,et al.  Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and$1/f$Noise , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Chien-Nan Jimmy Liu,et al.  Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  M. Takamiya,et al.  An on-chip 100 GHz-sampling rate 8-channel sampling oscilloscope with embedded sampling clock generator , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[15]  Hugh Thompson,et al.  An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[16]  Gu-Yeon Wei,et al.  A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25/spl mu/m CMOS , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[17]  Pavan Kumar Hanumolu,et al.  Supply-noise mitigation techniques in phase-locked loops , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

[18]  J. Wei,et al.  A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[19]  Gaetano Palumbo,et al.  A detailed analysis of power-supply noise attenuation in bandgap voltage references , 2003 .

[20]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .