ViPZonE: OS-level memory variability-driven physical address zoning for energy savings
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[1] Karthick Rajamani,et al. Benchmarking for Power and Performance , 2007 .
[2] Taewhan Kim,et al. Memory access scheduling and binding considering energy minimization in multi-bank memory systems , 2004, Proceedings. 41st Design Automation Conference, 2004..
[3] Michael Lang,et al. Analyzing the trade-off between multiple memory controllers and memory channels on multi-core processor performance , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).
[4] Gu-Yeon Wei,et al. Process Variation Tolerant 3T1D-Based Cache Architectures , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[5] Jun Yang,et al. Variation-tolerant non-uniform 3D cache management in die stacked multicore processor , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[6] Bruce Jacob,et al. DRAMSim2: A Cycle Accurate Memory System Simulator , 2011, IEEE Computer Architecture Letters.
[7] Narayanan Vijaykrishnan,et al. Working with Process Variation Aware Caches , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[8] Mihaela van der Schaar,et al. Software adaptation in quality sensitive applications to deal with hardware variability , 2010, GLSVLSI '10.
[9] Xuanyao Fong,et al. Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective , 2012, IEEE Sensors Journal.
[10] Karthick Rajamani,et al. Energy Management for Commercial Servers , 2003, Computer.
[11] Mahmut T. Kandemir,et al. Scheduler-based DRAM energy management , 2002, DAC '02.
[12] Csaba Andras Moritz,et al. Designing Memory Subsystems Resilient to Process Variations , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).
[13] Mahmut T. Kandemir,et al. Process-Variation-Aware Adaptive Cache Architecture and Management , 2009, IEEE Transactions on Computers.
[14] Kai Li,et al. The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[15] Xiaowei Li,et al. Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy , 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.
[16] Calvin Lin,et al. A comprehensive approach to DRAM power management , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[17] Xiaobo Sharon Hu,et al. Power aware variable partitioning and instruction scheduling for multiple memory banks , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[18] Mahmut T. Kandemir. Impact of data transformations on memory bank locality , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[19] Puneet Gupta,et al. A case for opportunistic embedded sensing in presence of hardware power variability , 2010 .
[20] Hannu Tenhunen,et al. Optimal memory controller placement for chip multiprocessor , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[21] Xin Li. Rethinking memory redundancy: Optimal bit cell repair for maximum-information storage , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).
[22] Ke Meng,et al. Process Variation Aware Cache Leakage Management , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.
[23] Robert Love,et al. Linux Kernel Development , 2003 .
[24] Nikil D. Dutt,et al. E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories , 2011, 2011 Design, Automation & Test in Europe.
[25] Sanjeev Kumar,et al. Dynamic tracking of page miss ratio curve for memory management , 2004, ASPLOS XI.
[26] Yu Cao,et al. Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[27] Kevin Skadron,et al. Impact of Process Variations on Multicore Performance Symmetry , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[28] Yifeng Zhu,et al. Evaluating memory energy efficiency in parallel I/O workloads , 2007, 2007 IEEE International Conference on Cluster Computing.
[29] Jun Yang,et al. A durable and energy efficient main memory using phase change memory technology , 2009, ISCA '09.
[30] Sung Woo Chung,et al. Selective wordline voltage boosting for caches to manage yield under process variations , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[31] Jung Ho Ahn,et al. Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs , 2009, IEEE Computer Architecture Letters.
[32] James Tschanz,et al. Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[33] Puneet Gupta,et al. Variability-aware duty cycle scheduling in long running embedded sensing systems , 2011, 2011 Design, Automation & Test in Europe.
[34] Puneet Gupta,et al. Power Variability in Contemporary DRAMs , 2012, IEEE Embedded Systems Letters.
[35] Keith A. Bowman,et al. Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).
[36] Zhao Zhang,et al. Mini-rank: Adaptive DRAM architecture for improving memory power efficiency , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[37] Somayeh Sardashti,et al. The gem5 simulator , 2011, CARN.
[38] Narayanan Vijaykrishnan,et al. Variation-aware task allocation and scheduling for MPSoC , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[39] Karthick Rajamani,et al. A performance-conserving approach for reducing peak power consumption in server systems , 2005, ICS '05.
[40] Puneet Gupta,et al. Variation-aware speed binning of multi-core processors , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).
[41] Kathryn S. McKinley,et al. Cooperative caching with keep-me and evict-me , 2005, 9th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT'05).
[42] Timothy Mattson,et al. A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[43] Puneet Gupta,et al. VaMV: Variability-aware Memory Virtualization , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[44] Chen Ding,et al. P-OPT: Program-Directed Optimal Cache Management , 2008, LCPC.
[45] Avesta Sasan,et al. Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[46] Doug Lea. The GNU C++ library , 1996 .