Simulating Static and Dynamic Faults in BIST Strucutres with a FPGA Based Emulator

Circuit emulation, using dynamically reconfigurable hardware is a high speed alternative to circuit simulation, especially for large and complex designs. Dynamic reconfiguration enhances the ability to efficiently analyse the test of combinational and sequential circuits by providing statistical information on fault grading, detectability, and signature analysis. In this paper we examine hardware accelleration of static and delay fault simulation, and the accelleration in simulating new BIST techniques.

[1]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[2]  Andrzej Krasniewski,et al.  Estimating testing effectiveness of the circular self-test path technique , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Vishwani D. Agrawal,et al.  A Tutorial on Built-In Self-Test, Part 2: Applications , 1993, IEEE Des. Test Comput..

[4]  Yervant Zorian,et al.  Programmable space compaction for BIST , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

[5]  Paul H. Bardell,et al.  Self-Testing of Multichip Logic Modules , 1982, International Test Conference.

[6]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[7]  Edward J. McCluskey,et al.  Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets , 1986, ITC.

[8]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[9]  Andrzej Krasniewski,et al.  Circular self-test path: a low-cost BIST technique for VLSI circuits , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Howard C. Card,et al.  Cellular automata-based pseudorandom number generators for built-in self-test , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Gernot Metze,et al.  A New Representation for Faults in Combinational Digital Circuits , 1972, IEEE Transactions on Computers.

[12]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[13]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[14]  Vishwani D. Agrawal,et al.  A Tutorial on Built-in Self-Test. I. Principles , 1993, IEEE Des. Test Comput..