Equalization techniques for high-speed serial interconnect transceivers

In this paper, the equalization techniques for high-speed interconnect transceivers are discussed. Serial interconnect transceivers have been widely adopted for its high data transfer rate, low cost, good noise immunity and low EMI. Signal SNR can be severely degraded by transmission channel. Effects due to channel impairments and tradeoffs among different equalization techniques are discussed in the paper. Implementation examples of key building blocks for high-speed serial transceiver in deep sub-micron CMOS logic process are also introduced.