Energy and switch area optimizations for FPGA global routing architectures
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[1] Yao-Wen Chang,et al. Generic Universal Switch Blocks , 2000, IEEE Trans. Computers.
[2] Andrew A. Chien,et al. Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization , 2005, 2005 International Conference on Computer Design.
[3] Jonathan Rose,et al. The Design of an SRAM-Based Field-Programmable Gate Array — Part I : Architecture , 1999 .
[4] Alexander Zelikovsky,et al. Multicommodity Flow Algorithms for Buffered Global Routing , 2007 .
[5] Dirk Stroobandt,et al. The interpretation and application of Rent's rule , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[6] Zvonko G. Vranesic,et al. Minimizing interconnection delays in array-based FPGAs , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.
[7] A. Ye,et al. Architecture of datapath-oriented coarse-grain logic and routing for FPGAs , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[8] Stephen D. Brown,et al. Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays , 1996, VLSI Design.
[9] J. P. Grossman,et al. Characterization and parameterized generation of synthetic combinational benchmark circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Jan M. Van Campenhout,et al. Toward the accurate prediction of placement wire length distributions in VLSI circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[11] Steven J. E. Wilton,et al. A detailed power model for field-programmable gate arrays , 2005, TODE.
[12] IV RobertC.Carden,et al. A global router using an efficient approximate multicommodity multiterminal flow algorithm , 1991, 28th ACM/IEEE Design Automation Conference.
[13] P. Chow,et al. The design of an SRAM-based field-programmable gate array. I. Architecture , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[14] Jonathan Rose,et al. Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits , 2005, FPGA '05.
[15] Chung-Kuan Cheng,et al. A global router with a theoretical bound on the optimal solution , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[16] Kurt Mehlhorn,et al. A Faster Approximation Algorithm for the Steiner Problem in Graphs , 1988, Inf. Process. Lett..
[17] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[18] Rui Shi,et al. Surfliner: a distortionless electrical signaling scheme for speed of light on-chip communications , 2005, 2005 International Conference on Computer Design.
[19] Vaughn Betz,et al. Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.
[20] Anthony J. Yu,et al. Directional and single-driver wires in FPGA interconnect , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).
[21] Raphael Rubin,et al. Design of FPGA interconnect for multilevel metallization , 2004, IEEE Trans. Very Large Scale Integr. Syst..
[22] Jochen Könemann,et al. Faster and simpler algorithms for multicommodity flow and other fractional packing problems , 1998, Proceedings 39th Annual Symposium on Foundations of Computer Science (Cat. No.98CB36280).
[23] Hai Zhou,et al. Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems , 2010 .
[24] Farhad Shahrokhi,et al. The maximum concurrent flow problem , 1990, JACM.
[25] Jason Cong,et al. FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[26] Christoph Albrecht,et al. Provably good global routing by a new approximation algorithm for multicommodity flow , 2000, ISPD '00.
[27] STEPHEN BROWN,et al. Minimizing FPGA Interconnect Delays , 1996, IEEE Des. Test Comput..
[28] Raphael Rubin,et al. Design of FPGA interconnect for multilevel metallization , 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[29] Jonathan Rose,et al. Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[30] Seokjin Lee,et al. Wire type assignment for FPGA routing , 2003, FPGA '03.
[31] Yi Zhu,et al. Communication latency aware low power NoC synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[32] Andrew B. Kahng,et al. Multicommodity Flow Algorithms for Buffered Global Routing , 2007, Handbook of Approximation Algorithms and Metaheuristics.
[33] W. Donath. Wire length distribution for placements of computer logic , 1981 .
[34] Chak-Kuen Wong,et al. A faster approximation algorithm for the Steiner problem in graphs , 1986, Acta Informatica.