The impact of PMOST bias-temperature degradation on logic circuit reliability performance

This work investigated the impact of pMOST bias-temperature (BT) degradation on logic product's speed (Fmax) and minimum allowed operating voltage (Vccmin). BT degradation occurs during the product Burn-In and under the normal circuit operation. The interaction of device degradation and circuit performance is explained. Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanism and degradation models are proposed to explain the interaction of fluorine with device and circuit reliability. Process optimization, such as fluorine implant, can be used to reduce the pMOST BT impact on circuit degradation. Reliability guardband in Fmax and Vccmin is recommended, as part of the production testing to ensure reliable logic product performance and functionality during the product's lifetime. A guardband methodology is also discussed in the paper.

[1]  S. Chaudhry,et al.  The effect of fluorine from BF2 source/drain extension implants on performance of PMOS transistors with thin gate oxides , 2001, IEEE Electron Device Letters.

[2]  P. Vande Voorde,et al.  Boron diffusion and penetration in ultrathin oxide with poly-Si gate , 1998, IEEE Electron Device Letters.

[3]  Yung-Huei Lee,et al.  Effect of pMOST bias-temperature instability on circuit reliability performance , 2003, IEEE International Electron Devices Meeting 2003.

[4]  T. Yamamoto,et al.  A new degradation mode of scaled p/sup +/ polysilicon gate pMOSFETs induced by bias temperature (BT) instability , 1995, Proceedings of International Electron Devices Meeting.

[5]  E. H. Nicollian,et al.  Mechanism of negative‐bias‐temperature instability , 1991 .

[6]  T. Mogami,et al.  Bias temperature instability in scaled p/sup +/ polysilicon gate p-MOSFET's , 1999 .

[7]  S. Prasad,et al.  Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate , 1998, IEEE Electron Device Letters.

[8]  H. Nakao,et al.  Fluorine implantation impact in extension region on the electrical performance of sub-50nm P-MOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[9]  Yung-Huei Lee,et al.  Effect of trench edge on pMOSFET reliability , 2001, Microelectron. Reliab..

[10]  James D. Plummer,et al.  Species and dose dependence of ion implantation damage induced transient enhanced diffusion , 1996 .

[11]  T. Kubota,et al.  Bias-temperature degradation of pMOSFETs: mechanism and suppression , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[12]  Anthony I. Chou,et al.  IMPROVEMENT OF ULTRATHIN GATE OXIDE AND OXYNITRIDE INTEGRITY USING FLUORINE IMPLANTATION TECHNIQUE , 1997 .

[13]  Ogawa,et al.  Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface. , 1995, Physical review. B, Condensed matter.

[14]  Kevin S. Jones,et al.  Fluorine effect on boron diffusion: chemical or damage? , 1998, 1998 International Conference on Ion Implantation Technology. Proceedings (Cat. No.98EX144).

[15]  S. Natarajan,et al.  Impact of negative bias temperature instability on digital circuit reliability , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[16]  S. Rauch.  The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs , 2002 .

[17]  J. Kavalieros,et al.  100 nm gate length high performance/low power CMOS transistor structure , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[18]  Terence B. Hook,et al.  The effects of fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology , 2001 .

[19]  Tahir Ghani,et al.  Source/drain extension scaling for 0.1 /spl mu/m and below channel length MOSFETs , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[20]  Shigeo Ogawa,et al.  Interface‐trap generation at ultrathin SiO2 (4–6 nm)‐Si interfaces during negative‐bias temperature aging , 1995 .