Declarative Programming Across the Undergraduate Curriculum

class REG_panel extends Panel { REG_panel (String name, String init) { setLayout(new BorderLayout()); add(new Label(name), BorderLayout.WEST); add(new Button(init), BorderLayout.EAST); } } class PC_panel extends REG_panel { PC_panel () { super("PC", "0"); } } class GT_panel extends REG_panel { GT_panel () { super("GT", "false"); } } class ACC_panel extends REG_panel { ACC_panel () { super("ACC", "0"); } } class IR_panel extends REG_panel { IR_panel () { super("IR", "STOP"); } } class EQ_panel extends REG_panel { EQ_panel () { super("EQ", "false"); } } class LT_panel extends REG_panel { LT_panel () { super("LT", "false"); } } The Java abstract window toolkit and more recently the Swing library offer many more declarative ways for specifying the layout of GUI components. The most sophisticated manager (GridBagLayout ) requires explicit geometric constraints to define the size, weight, and position of each component. The constraints are expressed as an instance of GridBagConstraints in what is essentially a separate little language. 2.5 Hardware Design Modern hardware description languages allow engineers to express the behavior of a hardware circuit at a high-level of abstraction. Once the design is deemed correct a structural description of the circuit that uses low-level gates and transistors is synthesized. In our terms the behavioral description of a hardware circuit is a declarative program that states what the circuit does but not how to construct it. As a simple example consider the problem of designing a 4-bit synchronous counter. The counter has one input: the clock, and one output: the current count. Initially the output should be 0, and then it should be incremented at every negative edge of the clock. In a hardware description language like Verilog it is possible to write a simple behavioral (declarative) description of the counter that can be used for simulation and verification [9]: module counter (ck, count); input ck; output count; reg [3:0] count; initial count = 0; always @(negedge ck) #10 count = count + 1; endmodule The counter module should be almost self-explanatory even for readers not familiar with Verilog. (See [3] for a precise operational semantics of behavioral Verilog.) The key thing to note about the the behavioral description of the circuit is that the increment operation of the counter is performed using the mathematical addition function+. In contrast a structural description of the counter would use low-level gates to realize the increment operation. Again in Verilog we would write [9]: module counter (ck, count); input ck;