Calibration Techniques for Digitally Assisted Nyquist-Rate ADCs

In recent years, the energy efficiency of ADCs has been continuously increasing due to the advances in integrated circuit technologies, circuit and architecture innovations, novelties in digital calibration, as well as improved CAD tools. With faster transistors in CMOS, the trend is to move in particular to higher sampling rates. CMOS is not only interesting because of the ease of combination of analog and digital circuits on the same substrate but also because of the extensive range of intellectual property (IP) available. As digital circuits fully benefit from the CMOS technology scaling due to improved transition frequencies of transistors, they are also less sensitive to noise, supply and process variations, compared to their analog counterparts. The use of these scaled transistors with minimum channel length and minimum oxide thickness to implement analog functions, adversely affects parameters relevant to analog design. Achieving high linearity, high sampling rate, and high dynamic range, with low supply voltages and low power dissipation is a major challenge in designing analog circuits. The technology scaling benefits of digital circuits are exploited in the presented ADC implementations in this thesis in order to reduce the complexity of ADCs in the analog domain and to enhance the precision of the converters using digital circuit techniques. For this reason, different digitally-assisted calibration and correction techniques are analyzed throughout this thesis which improve the energy efficiency of ADCs compared to the uncalibrated ones and the most effective ADCs are implemented in CMOS. This thesis focuses on Nyquist-rate high-speed ADC architectures with emphasis on successive approximation register (SAR) and folding ADCs. The SAR