Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches

In this paper, we comparatively evaluate the energy consumption of real-time and media benchmarks on three different hybrid on-chip memory architectures. Our evaluation indicates that while pure SPMs can lead to less on-chip memory energy consumption than pure caches of the same size, the pure caches can reduce total energy consumption than pure SPMs by improving the performance. The hybrid SPM-caches can further reduce the total energy consumption for both real-time and media benchmarks. In particular, we find using the hybrid SPM-caches for both instructions and data can maximally reduce the total energy dissipation.

[1]  Rajeev Barua,et al.  An optimal memory allocation scheme for scratch-pad-based embedded systems , 2002, TECS.

[2]  Neil C. Audsley,et al.  Studying the Applicability of the Scratchpad Memory Management Unit , 2010, 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium.

[3]  Sumesh Udayakumaran,et al.  Compiler-decided dynamic memory allocation for scratch-pad based embedded systems , 2003, CASES '03.

[4]  Vincenzo Catania,et al.  EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration , 2003, ESTImedia.

[5]  Mahmut T. Kandemir,et al.  Dataflow analysis for energy-efficient scratch-pad memory management , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[6]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[7]  B. R. Rau,et al.  HPL-PD Architecture Specification:Version 1.1 , 2000 .

[8]  Mei Chen,et al.  Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[9]  Lin Gao,et al.  Memory coloring: a compiler approach for scratchpad memory management , 2005, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05).

[10]  Peter Marwedel,et al.  Overlay techniques for scratchpad memories in low power embedded processors , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Wei Zhang,et al.  Hybrid SPM-cache architectures to achieve high time predictability and performance , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

[12]  Peter Marwedel,et al.  Assigning program and data objects to scratchpad for energy reduction , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[13]  Gerard J. M. Smit,et al.  A mathematical approach towards hardware design , 2010, Dynamically Reconfigurable Architectures.

[14]  Peter Marwedel,et al.  Cache-aware scratchpad allocation algorithm , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[15]  Hui Wu,et al.  Optimal WCET-aware code selection for scratchpad memory , 2010, EMSOFT '10.

[16]  Alexander G. Dean,et al.  Leveraging both Data Cache and Scratchpad Memory through Synergetic Data Allocation , 2012, 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium.

[17]  Nikil D. Dutt,et al.  Efficient utilization of scratch-pad memory in embedded processor applications , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[18]  Peter Marwedel,et al.  Scratchpad memory: a design alternative for cache on-chip memory in embedded systems , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[19]  Rajeev Barua,et al.  Scratch-pad memory allocation without compiler support for java applications , 2007, CASES '07.

[20]  Heiko Falk,et al.  Optimal static WCET-aware scratchpad allocation of program code , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[21]  Kanad Ghose,et al.  Analytical energy dissipation models for low-power caches , 1997, ISLPED '97.

[22]  Jason Cong,et al.  An energy-efficient adaptive hybrid cache , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[23]  Wei-Che Tseng,et al.  Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory , 2011, 2011 Design, Automation & Test in Europe.

[24]  Jan Gustafsson,et al.  The Mälardalen WCET Benchmarks: Past, Present And Future , 2010, WCET.

[25]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[26]  Ting Chen,et al.  WCET centric data allocation to scratchpad memory , 2005, 26th IEEE International Real-Time Systems Symposium (RTSS'05).

[27]  Jaehyuk Huh,et al.  Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture , 2003, ISCA '03.

[28]  Sharad Malik,et al.  Performance Analysis of Embedded Software Using Implicit Path Enumeration , 1995, 32nd Design Automation Conference.

[29]  Heonshik Shin,et al.  Scratchpad memory management for portable systems with a memory management unit , 2006, EMSOFT '06.

[30]  Mahmut T. Kandemir,et al.  Compiler-directed scratch pad memory optimization for embedded multiprocessors , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[31]  Mahmut T. Kandemir,et al.  Banked scratch-pad memory management for reducing leakage energy consumption , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[32]  Jean-François Deverge,et al.  WCET-Directed Dynamic Scratchpad Memory Allocation of Data , 2007, 19th Euromicro Conference on Real-Time Systems (ECRTS'07).