Simulation and analysis of negative-bias temperature instability aging on power analysis attacks
暂无分享,去创建一个
[1] D. Varghese,et al. A comprehensive model for PMOS NBTI degradation: Recent progress , 2007, Microelectron. Reliab..
[2] Elena Trichina,et al. Combinational Logic Design for AES SubByte Transformation on Masked Data , 2003, IACR Cryptol. ePrint Arch..
[3] Thomas Zefferer,et al. Evaluation of the Masked Logic Style MDPL on a Prototype Chip , 2007, CHES.
[4] Stefan Mangard,et al. Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints , 2005, CHES.
[5] Zhimin Chen,et al. Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage , 2006, CHES.
[6] Ingrid Verbauwhede,et al. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[7] Wayne P. Burleson,et al. Analysis and mitigation of process variation impacts on Power-Attack Tolerance , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[8] Bart Preneel,et al. Mutual Information Analysis , 2008, CHES.
[9] Yu Cao,et al. Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.
[10] Christophe Clavier,et al. Correlation Power Analysis with a Leakage Model , 2004, CHES.
[11] Francky Catthoor,et al. NBTI Monitoring and Design for Reliability in Nanoscale Circuits , 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
[12] Denis Flandre,et al. A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices , 2011, EUROCRYPT.
[13] Tao Jin,et al. Combating NBTI-induced aging in data caches , 2013, GLSVLSI '13.
[14] Christof Paar,et al. Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[15] Pankaj Rohatgi,et al. Introduction to differential power analysis , 2011, Journal of Cryptographic Engineering.
[16] Andrey Bogdanov,et al. PRESENT: An Ultra-Lightweight Block Cipher , 2007, CHES.
[17] Stefan Mangard,et al. Side-Channel Leakage of Masked CMOS Gates , 2005, CT-RSA.
[18] Pankaj Rohatgi,et al. Template Attacks , 2002, CHES.
[19] Mark G. Karpovsky,et al. Power attacks on secure hardware based on early propagation of data , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).
[20] V. Reddy,et al. A comprehensive framework for predictive modeling of negative bias temperature instability , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.
[21] Yu Cao,et al. The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[22] H. Kufluoglu,et al. A Generalized Reaction–Diffusion Model With Explicit H– $\hbox{H}_{2}$ Dynamics for Negative-Bias Temperature-Instability (NBTI) Degradation , 2007, IEEE Transactions on Electron Devices.
[23] Muhammad Ashraful Alam,et al. A comprehensive model of PMOS NBTI degradation , 2005, Microelectron. Reliab..