As SRAM arrays become lithographically more aggressive than random logic, they are more and more determining the lithography processes used. High yielding, low leakage, dense SRAM cells demand fairly aggressive lithographic process conditions. This leads to a borderline process window for logic devices. The tradeoff obtained between process window optimization for random logic gates and dense SRAM is not always straightforward, and sometimes necessitates design rule and layout modifications. By delinking patterning of the logic devices from SRAM, one can optimize the patterning processes for these devices independently. This can be achieved by a special double patterning technique that employs a combination of double exposure and double etch (DE2). In this paper we show how a DE2 patterning process can be employed to pattern dense SRAM cells in the 45nm node on fully integrated wafers, with more than adequate overlap of gate line-end onto active area. We have demonstrated that this process has adequate process window for sustainable manufacturing. For comparison purpose we also demonstrate a single exposure single etch solution to treat such dense SRAM cells. In 45nm node, the dense SRAM cell can also be printed with adequate tolerances and process window with single expose (SE) with optimized OPC. This is confirmed by electrical results on wafer. We conclude that DE2 offers an attractive alternative solution to pattern dense SRAM in 45nm and show such a scheme can be extended to 32nm and beyond. Employing DE2 lets designers migrate to very small tip-to-tip distance in SRAM. The selection of DE2 or SE depends on layout, device performance requirements, integration schemes and cost of ownership.