A nested digital delta-sigma modulator architecture for fractional-N frequency synthesis

A nested digital delta-sigma modulator (DDSM) architecture for fractional-N frequency synthesis is investigated and compared with the conventional MASH 1-1-1 DDSM. In the nested architecture, the LSBs of the input word are processed by a first-order DDSM and added to the MSBs before being processed by a third-order DDSM. Using the error masking design methodology [1], rules for selecting the optimum wordlengths are presented. We show that the nested architecture requires 15% fewer flip-flops and 13% fewer full-adders than the conventional architecture, resulting in an overall hardware saving of 15%. Simulation results confirm the analytical predictions.

[1]  D. A. Rich,et al.  A minimal multibit digital noise shaping architecture , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[2]  Juha Kostamovaara,et al.  A practical Δ-Σ modulator design method based on periodical behavior analysis. , 2005 .

[3]  K. Hosseini,et al.  Mathematical analysis of digital MASH delta-sigma modulators for fractional-N frequency synthesizers , 2006, 2006 Ph.D. Research in Microelectronics and Electronics.

[4]  Sleiman Bou-Sleiman,et al.  Optimal $ \Sigma \Delta$ Modulator Architectures for Fractional-$ {N}$ Frequency Synthesis , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Zhipeng Ye,et al.  Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Izzet Kale,et al.  A pipelined noise shaping coder for fractional-N frequency synthesis , 2001, IEEE Trans. Instrum. Meas..

[7]  Saul Rodriguez,et al.  Optimal Modulator Architectures for Fractional- Frequency Synthesis , 2010 .

[8]  Ian Galton,et al.  Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[9]  Calvin Plett,et al.  Integrated Circuit Design for High-Speed Frequency Synthesis , 2006 .

[10]  Sudhakar Pamarti.  Digital techniques for integrated frequency synthesizers: A tutorial , 2009, IEEE Communications Magazine.

[11]  Franco Maloberti,et al.  ΔΣ time interleaved current steering DAC with dynamic elements matching , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[12]  K.J. Wang,et al.  Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL , 2008, IEEE Journal of Solid-State Circuits.