Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devices

It was found that, as the channel length decreased, the threshold voltage shift caused by drain-induced barrier lowering (DIBL) first increased with increasing substrate bias and then decreased as the channel length decreased further. The channel length (L/sub INT/) corresponding to an almost zero change of the DIBL variation with substrate bias was found to be between 0.78 and 0.90 mu m for the PMOS devices. This change in DIBL with substrate bias for devices with varying L can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, an empirical model for describing this substrate bias characteristic of the DIBL effect is developed. >

[1]  R. Troutman,et al.  Subthreshold characteristics of insulated-gate field-effect transistors , 1973 .

[2]  T. Skotnicki,et al.  Anomalous Punchthrough in ULSI Buried-channel P-MOSFETs , 1989, ESSDERC '89: 19th European Solid State Device Research Conference.

[3]  J. Meindl,et al.  Performance limits of CMOS ULSI , 1985, IEEE Transactions on Electron Devices.

[4]  Andrei Vladimirescu,et al.  The Simulation of MOS Integrated Circuits Using SPICE2 , 1980 .

[5]  M. Koyanagi,et al.  Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFET's , 1987, IEEE Transactions on Electron Devices.

[6]  Siegfried Selberherr,et al.  Low temperature MOS device modeling , 1989, Proceedings of the Workshop on Low Temperature Semiconductor Electronics,.

[7]  R.H. Dennard,et al.  1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications , 1979, IEEE Transactions on Electron Devices.

[8]  R. R. Troutman,et al.  VLSI limitations from drain-induced barrier lowering , 1979 .

[9]  J. Woo,et al.  Short-channel effects in MOSFET's at liquid-Nitrogen temperature , 1986, IEEE Transactions on Electron Devices.

[10]  J. Y. Chen,et al.  Punchthrough current for submicrometer MOSFETs in CMOS VLSI , 1988 .

[11]  H. Masuda,et al.  Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect , 1979, IEEE Transactions on Electron Devices.

[12]  H. Mingam,et al.  Surface mobility in n/sup +/ and p/sup +/ doped polysilicon gate PMOS transistors , 1989 .

[13]  G. Taylor.  Subthreshold conduction in MOSFET's , 1978, IEEE Transactions on Electron Devices.

[14]  D. Kwong,et al.  Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's , 1984, IEEE Electron Device Letters.

[15]  S.G. Chamberlain,et al.  Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations , 1986, IEEE Transactions on Electron Devices.

[16]  B. Hoefflinger,et al.  A parametric short-channel MOS transistor model for subthreshold and strong inversion current , 1984, IEEE Journal of Solid-State Circuits.

[17]  R. Troutman.  Subthreshold design considerations for insulated gate field-effect transistors , 1973 .

[18]  R. Troutman,et al.  Simple model for threshold voltage in a short-channel IGFET , 1977, IEEE Transactions on Electron Devices.