A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol

This paper presents the first SerDes design to demonstrate a PCI-Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285 um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and clocking, power management including power gating for all analog blocks, continuous data rate support between 1–32 Gb/s, and supporting channel topologies with insertion loss up to 37dB at 16GHz with BER < 1e-12 in 10nm process technology.

[1]  C. Auth,et al.  A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[2]  Eisse Mensink,et al.  A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  Keiichi Higeta,et al.  3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[4]  Dmitry Petrov,et al.  6.2 A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

[5]  William Song,et al.  A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[6]  Takayuki Shibasaki,et al.  3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[7]  Junho Cho,et al.  A fully-adaptive wideband 0.5–32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology , 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

[8]  Fulvio Spagna.  Clock and data recovery systems , 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).