A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 67dB dynamic range in 10MHz bandwidth

A 2-2 cascaded /spl Sigma//spl Delta/ modulator with continuous-time loop filters and 4b quantizers is presented. The dynamic range is 67dB in a 10MHz bandwidth at a 160MS/s with a full-scale input range of 200mV/sub rms/. Inherent anti-aliasing filtering is over 50dB. The 0.18/spl mu/m CMOS chip measures 1.7mm/sup 2/ and draws 68mA from a 1.8V supply.

[1]  R. V. Veldhoven A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, IEEE J. Solid State Circuits.

[2]  Beomsup Kim,et al.  A hybrid delta-sigma modulator with adaptive calibration , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[3]  E.J. van der Zwan,et al.  A 0.2 mW CMOS /spl Sigma//spl Delta/ modulator for speech coding with 80 dB dynamic range , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[4]  T. Burger,et al.  A 13.5mW, 185 MSample/s /spl Delta//spl Sigma/-modulator for UMTS/GSM dual-standard IF reception , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  Chi-Hung Lin,et al.  Synthesis and analysis of high-order cascaded continuous-time /spl Sigma//spl Delta/ modulators , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[6]  M. Zargari,et al.  A dual channel /spl Sigma//spl Delta/ ADC with 40MHz aggregate signal bandwidth , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[7]  Gert Cauwenberghs,et al.  Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration , 2000 .

[8]  L. Longo,et al.  A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio , 2000, IEEE Journal of Solid-State Circuits.

[9]  R. Schreier,et al.  Delta-sigma modulators employing continuous-time circuitry , 1996 .

[10]  Atsushi Iwata,et al.  A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping , 1987 .

[11]  Maurits Ortmanns,et al.  On the synthesis of cascaded continuous-time Sigma-Delta modulators. , 2001 .

[12]  W. Snelgrove,et al.  Excess loop delay in continuous-time delta-sigma modulators , 1999 .