Hierarchical test pattern generation based on high-level primitives

It is demonstrated that the exploitation of high-level primitives (HLPs) and, in particular, of the knowledge concerning their function in ATPG (automatic test pattern generation) leads to significant improvements in implication, unique sensitization, and multiple backtrace. Motivated by this observation and the necessity of covering all faults inside HLPs, the authors present the extension of the ATPG system SOCRATES to hierarchical test pattern generation, which is based upon HLPs and the strategy of dynamically expanding the HLPs to their gate-level realization, at most one at a time. Experimental results have substantiated that the proposed approach performs significantly better in terms of CPU time, elapsed time, fault coverage, and memory requirements than a gate-level ATPG algorithm. It is expected that the extended SOCRATES algorithm will be capable of coping with circuits consisting of 100000 gates and more within reasonable times, even in a workstation environment.<<ETX>>

[1]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[2]  Prabhakar Goel,et al.  PODEM-X: An Automatic Test Generation System for VLSI Logic Structures , 1981, 18th Design Automation Conference.

[3]  Mats Johansson The GENESYS-Algorithm for ATPG without Fault Simulation , 1983, ITC.

[4]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Premachandran R. Menon,et al.  Test Generation In Lamp2: Concepts and Algorithms , 1985, ITC.

[6]  Robert Hum,et al.  Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing , 1984, ITC.

[7]  Eduard Cerny Controllability and Fault Observability in Modular Combinational Circuits , 1978, IEEE Transactions on Computers.

[8]  F. Brglez,et al.  Hierarchical fault simulation in combinational circuits , 1989, [1989] Proceedings of the 1st European Test Conference.

[9]  Erwin Trischler ATWIG, An Automatic Test Pattern Generator with Inherent Guidance , 1984, ITC.

[10]  Kurt Antreich,et al.  Accelerated Fault Simulation and Fault Grading in Combinational Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  John P. Hayes,et al.  Hierarchical test generation using precomputed tests for modules , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  John P. Hayes,et al.  Hierarchical test generation using precomputed testsd for modules , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[13]  Michael H. Schulz,et al.  Advanced automatic test pattern generation and redundancy identification techniques , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[14]  Melvin A. Breuer,et al.  Functional Level Primitives in Test Generation , 1980, IEEE Transactions on Computers.

[15]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[16]  Paolo Prinetto,et al.  Testing Strategy and Technique for Macro-Based Circuits , 1985, IEEE Transactions on Computers.

[17]  Janak H. Patel,et al.  A Hierarchical Approach to Test Vector Generation , 1987, 24th ACM/IEEE Design Automation Conference.