Avalanche Reliability of Planar-gate SiC MOSFET with Varied JFET Region Width and Its Balance with Characteristic Performance

In this work, the influence of JFET region width on 1200V SiC MOSFET’s avalanche reliability is studied with unclamped inductive switching (UIS) test. It is revealed that the highest avalanche capability is achieved with a JFET region width of 4μm. As presented in TCAD silmulation, locallized heat accumulation arising from high channel current density proves to be the failure mechanism. Furthermore, the balance between device performance and reliability with different JFET region width design is discussed by considering the device’s figure of merits (FOM).

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