Output buffer with on-chip compensation circuit

An LV-CMOS output buffer with on-chip process and temperature variation compensation of the MOSFET is described. The compensation data acquisition circuit and output buffers are prepared in the I/O (input/output) buffer area of the half-micron CMOS ASIC (application-specific integrated circuit). The compensation circuit can control the channel width of the final stage MOSFET in the output buffer from 60% to 140% of typical process condition requirements with 13% resolution. By using the compensation circuit, the variation of propagation delay is within /spl plusmn/15% of the center value. In addition, di/dt at output signal switching is reduced. These features help ASIC users to design with timing-critical interchip communications and with high density packages.