2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers

This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50Ω differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of −25dBm for a BER= 10−12 and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dBΩ, 1.5GHz bandwidth and occupies a chip area of 0.16mm2. The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.

[1]  Michiel Steyaert,et al.  A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode , 2010, 2010 Proceedings of ESSCIRC.

[2]  Reza Abdolvand,et al.  A 76dBΩ 1.7GHz 0.18µm CMOS tunable transimpedance amplifier using broadband current pre-amplifier for high frequency lateral micromechanical oscillators , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[3]  Horst Zimmermann,et al.  A highly sensitive 2.5 Gb/s transimpedance amplifier in CMOS technology , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[4]  Sung Min Park,et al.  1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications , 2004, IEEE Journal of Solid-State Circuits.

[5]  Sung Min Park,et al.  A 2.5Gb/s ESD-protected dual-channel optical transceiver array , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[6]  B. Nauta,et al.  Wide-band CMOS low-noise amplifier exploiting thermal noise canceling , 2004, IEEE Journal of Solid-State Circuits.