GPS 수신기용 0.13㎛ CMOS RF Front-End 회로 설계

This paper presents a RF receiver for GPS application in 0.13㎛ CMOS technology. The receiver is based on a 4.092㎒ low-IF architecture to alleviate the DC-offset problem. It includes a Low Noise Amplifier(LNA), a down conversion mixer. The whole receiver dissipates 8.4㎽ with 1.2V supply. And the system noise figure is(NF) 3.9㏈.