Regularity-Oriented Analog Placement with Conditional Design Rules
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Takao Ito | Masahiro Kawakita | Shigetoshi Nakatake | Masahiro Kojima | Michiko Kojima | Kenji Izumi | Tadayuki Habasaki
[1] Florin Balasa,et al. On the exploration of the solution space in analog placement with symmetry constraints , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Yoji Kajitani,et al. Multi-level placement with circuit schema based clustering in analog IC layouts , 2004 .
[3] Yoji Kajitani,et al. Module packing based on the BSG-structure and IC layout applications , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Florin Balasa,et al. Symmetry within the sequence-pair representation in the context ofplacement for analog design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Yao-Wen Chang,et al. TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans , 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Yoji Kajitani,et al. A device-level placement with multi-directional convex clustering , 2004, GLSVLSI '04.
[7] Yao-Wen Chang,et al. B*-Trees: a new representation for non-slicing floorplans , 2000, DAC.
[8] Takeshi Yoshimura,et al. An O-tree representation of non-slicing floorplan and its applications , 1999, DAC '99.
[9] Shigetoshi Nakatake. Structured Placement with Topological Regularity Evaluation , 2007 .
[10] Yoji Kajitani,et al. Space-planning: placement of modules with controlled empty area by single-sequence , 2004 .
[11] Evangeline F. Y. Young,et al. Analog Placement with Symmetry and Other Placement Constraints , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[12] Yoji Kajitani,et al. VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..