Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling, limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise, temperature variation, and aging, and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%–18% total dynamic power savings for logic blocks in 10-nm CMOS.

[1]  Saurabh Dighe,et al.  A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[2]  Jie Gu,et al.  A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  David Blaauw,et al.  8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[4]  Nasser A. Kurd,et al.  A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor , 2001, IEEE J. Solid State Circuits.

[5]  Sang H. Dhong,et al.  A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC , 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

[6]  James Tschanz,et al.  Characterization of PVT variation & aging induced hold time margins of flip-flop arrays at NTV in 22nm tri-gate CMOS , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[7]  Phillip Restle,et al.  26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[8]  Mingoo Seok,et al.  R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[9]  Samuel D. Naffziger,et al.  The implementation of the next-generation 64b itanium microprocessor , 2002 .

[10]  Dennis Sylvester,et al.  Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[11]  Hong Wang,et al.  An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[12]  Yong Kim,et al.  The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking , 2015, IEEE Journal of Solid-State Circuits.