A Novel Incremental Floorplan Algorithm for Duplication in Integration of High-level Synthesis and Floorplan

With VLSI advancing into deep submicron technology stage, interconnection delay has been the dominated aspect of timing issues. In this paper, we contrive a duplication method in high-level synthesis for interconnect delay optimization and present a new incremental floorplan algorithm integrating high-level synthesis with floorplan for exerting those duplication schemes. The new algorithm has been proved by experiments significantly decreasing the total wirelength and the critical path wirelength over the initial results with a linear time complexity. At the same time, the area has increased slightly and the area usage is even improved.

[1]  Jason Cong,et al.  Incremental physical design , 2000, ISPD '00.

[2]  Daniel Gajski,et al.  Introduction to high-level synthesis , 1994, IEEE Design & Test of Computers.

[3]  Martin D. F. Wong,et al.  Efficient Floorplan Area Optimization , 1989, 26th ACM/IEEE Design Automation Conference.

[4]  Majid Sarrafzadeh,et al.  An incremental floorplanner , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[5]  Ankur Srivastava,et al.  Timing driven gate duplication in technology independent phase , 2001, ASP-DAC '01.

[6]  Alice C. Parker,et al.  3D scheduling: high-level synthesis with floorplanning , 1991, 28th ACM/IEEE Design Automation Conference.

[7]  Qiang Zhou,et al.  Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[8]  Yici Cai,et al.  Corner block list: an effective and efficient topological representation of non-slicing floorplan , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[9]  Ankur Srivastava,et al.  Timing driven gate duplication , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.