Mapping of cores on to diagonal mesh-based network-on-chip
暂无分享,去创建一个
[1] David S. Johnson,et al. Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .
[2] Radu Marculescu,et al. Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] Luca Benini,et al. Analysis of power consumption on switch fabrics in network routers , 2002, DAC '02.
[4] Srinivasan Murali,et al. Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[5] An-Yeu Wu,et al. A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[6] Radu Marculescu,et al. Energy-aware mapping for tile-based NoC architectures under performance constraints , 2003, ASP-DAC '03.
[7] Coniferous softwood. GENERAL TERMS , 2003 .
[8] Jinwen Li,et al. An energy-aware heuristic constructive mapping algorithm for Network on Chip , 2009, 2009 IEEE 8th International Conference on ASIC.
[9] Ahmad Khademzadeh,et al. CGMAP: a new approach to Network-on-Chip mapping problem , 2009, IEICE Electron. Express.
[10] K. Wendy Tang,et al. Diagonal and Toroidal Mesh Networks , 1994, IEEE Trans. Computers.
[11] Mitsuo Gen,et al. Genetic algorithms and engineering optimization , 1999 .
[12] Ahmad Khademzadeh,et al. Chain-Mapping for mesh based Network-on-Chip architecture , 2009, IEICE Electron. Express.
[13] Vincenzo Catania,et al. A methodology for design of application specific deadlock-free routing algorithms for NoC systems , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[14] Federico Silla,et al. On the development of a communication-aware task mapping technique , 2004, J. Syst. Archit..
[15] Ahmad Khademzadeh,et al. Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip , 2009, IEICE Electron. Express.
[16] Majid Janidarmian,et al. Application-Specific Networks-on-Chips Design , 2011 .
[17] Eric R. Ziegel,et al. Genetic Algorithms and Engineering Optimization , 2002, Technometrics.
[19] Ahmad Khademzadeh,et al. Sorena: New on Chip Network Topology Featuring Efficient Mapping and Simple Deadlock Free Routing Algorithm , 2010, 2010 10th IEEE International Conference on Computer and Information Technology.