Integrated Power-Gating and State Assignment for Low Power FSM Synthesis

Power-gating is an effective technique for reducing standby leakage power and dynamic power. In power-gating one can shut off the power supply to sections of logic block while keeping other logic blocks active. However, careful design is required to make power-gating technique effective, otherwise, negative effect of power-gating may overwhelm the potential gain. In this paper we have presented the state partitioning and state encoding strategy targeting low power finite state machine (FSM) decomposition based on genetic algorithmic approach. All the previous works dealt only FSM partitioning but did not consider state encoding together. This is the first ever approach considering FSM partitioning and state encoding together in power-gating technique. Experimental result shows that upto 73% power saving can be done giving small amount of area penalty.

[1]  Yinshui Xia,et al.  Genetic algorithm based state assignment for power and area optimisation , 2002 .

[2]  Margus Kruus,et al.  Synthesis of Sequential Circuits with Dynamic Power Management , 2005 .

[3]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.

[4]  José C. Monteiro,et al.  Finite state machine decomposition for low power , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[5]  Reiner Kolla,et al.  Spanning tree based state encoding for low power dissipation , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[6]  Alberto L. Sangiovanni-Vincentelli,et al.  MUSTANG: state assignment of finite state machines targeting multilevel logic implementations , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  TingTing Hwang,et al.  Low power realization of finite state machines—a decomposition approach , 1996, TODE.

[8]  Gustavo Sutter,et al.  FSM Decomposition for Low Power in FPGA , 2002, FPL.

[9]  Yici Cai,et al.  FSM decomposition for power gating design automation in sequential circuits , 2005, 2005 6th International Conference on ASIC.

[10]  D. E. Goldberg,et al.  Genetic Algorithms in Search , 1989 .

[11]  Santanu Chattopadhyay,et al.  Finite state machine state assignment targeting low power consumption , 2004 .

[12]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.

[13]  Massoud Pedram,et al.  Low power synthesis of finite state machines with mixed D and T flip-flops , 2003, ASP-DAC '03.

[14]  Luca Benini,et al.  State assignment for low power dissipation , 1995 .

[15]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[16]  A. Despain,et al.  Low Power State Assignment Targeting Two- And Multi-level Logic Implementations , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[17]  Akhilesh Tyagi,et al.  Low power FSM design using Huffman-style encoding , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[18]  Irith Pomeranz,et al.  GALLOP: genetic algorithm based low power FSM synthesis by simultaneous partitioning and state assignment , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[19]  Kaushik Roy,et al.  SYCLOP: synthesis of CMOS logic for low power applications , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[20]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[21]  M. K. Dhodhi,et al.  State assignment of finite-state machines , 2000 .

[22]  Santanu Chattopadhyay,et al.  Low power state assignment and flipflop selection for finite state machine synthesis: a genetic algorithmic approach , 2001 .