A Cu/low-/spl kappa/ dual damascene interconnect for high performance and low cost integrated circuits

Copper and a low dielectric constant (low-/spl kappa/) material have been successfully integrated in a dual damascene interconnect architecture. The low-/spl kappa/ material (/spl kappa/=2.2) was used as intra-level dielectric and inter-level dielectric, which has led to significant reduction in both intra-level and inter-level capacitance. In addition, low Cu wiring resistance and low Cu via resistance have been achieved in the dual damascene interconnect which offers process simplification and low cost.

[1]  R. Havemann,et al.  Damascene integration of copper and ultra-low-k xerogel for high performance interconnects , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[2]  S. Das,et al.  A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[3]  P. Roper,et al.  Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[4]  Y. Hayashi,et al.  A degradation-free Cu/HSQ damascene technology using metal mask patterning and post-CMP cleaning by electrolytic ionized water , 1997, International Electron Devices Meeting. IEDM Technical Digest.