Managing a reconfigurable processor in a general purpose workstation environment

Reconfigurable processor hybrids are becoming an accepted solution in the embedded systems domain, but have yet to gain acceptance in the general purpose workstation domain. One problem with current solutions is their lack of support for the dynamic workloads and resource demands of a general purpose workstation. In this paper we describe and demonstrate a reconfigurable processor architecture that lets the operating system dynamically share the Field Programmable Logic (FPL) resource between a set of applications without the management overheads negating the benefit of having the extra resource.

[1]  Scott Hauck,et al.  Configuration prefetch for single context reconfigurable coprocessors , 1998, FPGA '98.

[2]  Laszlo A. Belady,et al.  A Study of Replacement Algorithms for Virtual-Storage Computer , 1966, IBM Syst. J..

[3]  Anoop Gupta,et al.  The impact of architectural trends on operating system performance , 1995, SOSP.

[4]  Jonathan M. Smith,et al.  FPGA Viruses , 1999, FPL.

[5]  Brent E. Nelson,et al.  Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing , 1999, FPL.

[6]  Michael Winston Dales The Proteus Processor - A Conventional CPU with Reconfigurable Functionality , 1999, FPL.

[7]  Ronald L. Rivest,et al.  The MD5 Message-Digest Algorithm , 1992, RFC.

[8]  Steffen Köhler,et al.  Prototyping Framework for Reconfigurable Processors , 2001, FPL.

[9]  Simon Thompson,et al.  Haskell: The Craft of Functional Programming , 1996 .

[10]  Abraham Silberschatz,et al.  Operating System Concepts , 1983 .

[11]  Seung-Soon Im,et al.  Tool interface standard (TIS) executable and linking format (ELF) specification , 1995 .

[12]  Mark de Wit,et al.  A dynamic reconfiguration run-time system , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[13]  Steven A. Guccione,et al.  Automated extraction of run-time parameterisable cores from programmable device configurations , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[14]  Rainer G. Spallek,et al.  CoMPARE: A Simple Reconfigurable Processor Architecture Exploiting Instruction Level Parallelism , 1998 .

[15]  Seth Copen Goldstein,et al.  Configuration Caching and Swapping , 2001, FPL.

[16]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[17]  Satnam Singh,et al.  PostscriptTM rendering with virtual hardware , 1997, FPL.

[18]  Bruce Schneier,et al.  The Twofish encryption algorithm: a 128-bit block cipher , 1999 .

[19]  Jerome H. Saltzer Naming and Binding of Objects , 1978, Advanced Course: Operating Systems.

[20]  Ralph Wittig,et al.  OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[21]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[22]  I. Xilinx Virtex series configuration architecture user guide , 2000 .

[23]  Robin Fairbairns,et al.  The Design and Implementation of an Operating System to Support Distributed Multimedia Applications , 1996, IEEE J. Sel. Areas Commun..

[24]  Gordon J. Brebner,et al.  A Virtual Hardware Operating System for the Xilinx XC6200 , 1996, FPL.

[25]  Jeffrey S. Chase,et al.  Opal: A Single Address Space System for 64-bit Architectures , 1992, OPSR.

[26]  Robert Magnus,et al.  Linux Kernel Internals , 1996 .

[27]  Brad L. Hutchings,et al.  A dynamic instruction set computer , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[28]  Zhiyuan Li,et al.  Configuration Caching Techniques for FPGA , 2000 .

[29]  Reiner W. Hartenstein,et al.  A Novel Compilation Technique for a Machine Paradigm based on Field-Programmable Logic , 1991 .

[30]  Michael Winston Dales Initial Analysis of the Proteus Architecture , 2001, FPL.

[31]  Michael J. Wirthlin,et al.  The Nano Processor: a low resource reconfigurable processor , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[32]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.

[33]  Margo I. Seltzer,et al.  A Comparison of OS Extension Technologies , 1996, USENIX Annual Technical Conference.

[34]  Satnam Singh,et al.  Rendering Postscript Fonts on FPGAs , 1999, FPL.

[35]  Richard Black,et al.  Explicit Network Scheduling , 1994 .

[36]  Thomas F. Melham,et al.  Formally Analyzed Dynamic Synthesis of Hardware , 2004, The Journal of Supercomputing.

[37]  Reiner W. Hartenstein,et al.  Xputers: An Open Family of Non-Von Neumann Architectures , 1990, ARCS.

[38]  Paul Chow,et al.  The effect of reconfigurable units in superscalar processors , 2001, FPGA.

[39]  Dean M. Tullsen,et al.  Simultaneous multithreading: Maximizing on-chip parallelism , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[40]  Mark Russinovich,et al.  Inside Microsoft Windows 2000 , 2000 .

[41]  Reiner W. Hartenstein,et al.  Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications , 1999 .

[42]  Oliver Diessel,et al.  Chip-Based Reconfigurable Task Management , 2001, FPL.

[43]  Stefan H.-M. Ludwig,et al.  Implementing Photoshop Filters in Virtex , 1999, FPL.

[44]  Vivek Sarkar,et al.  Baring It All to Software: Raw Machines , 1997, Computer.

[45]  Adam Donlin,et al.  Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry , 1998, FPL.

[46]  Keith Bostic,et al.  The design and implementa-tion of the 4.4BSD operating system , 1996 .

[47]  Juan Manuel Moreno,et al.  Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor , 1997, FPL.

[48]  Mark Shand,et al.  A case study of algorithm implementation in reconfigurable hardware and software , 1997, FPL.

[49]  Steven A. Guccione,et al.  XBI: a Java-based interface to FPGA hardware , 1998, Other Conferences.