This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.
[1]
Daniel G. Schweikert,et al.
LTX - a system for the directed automatic design of LSI circuits
,
1976,
DAC.
[2]
C. Y. Lee.
An Algorithm for Path Connections and Its Applications
,
1961,
IRE Trans. Electron. Comput..
[3]
Tokinori Kozawa,et al.
Advanced LILAC - an Automated Layout Generation system for MOS/LSIs
,
1974,
DAC '74.
[4]
Dave Hightower.
A solution to line-routing problems on the continuous plane
,
1969,
DAC '69.
[5]
Tokinori Kozawa,et al.
Block and track method for automated layout generation of MOS-LSI arrays
,
1972
.
[6]
Akihiro Hashimoto,et al.
Wire routing by optimizing channel assignment within large apertures
,
1971,
DAC.
[7]
Brian W. Kernighan,et al.
An optimum channel-routing algorithm for polycell layouts of integrated circuits
,
1973,
DAC '73.
[8]
Roland L. Mattison.
A high quality, low cost router for MOS/LSI
,
1972,
DAC '72.