Debugging multi-core systems-on-chip

5.

[1]  Bart Vermeulen,et al.  Silicon debug: scan chains alone are not enough , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[2]  Leslie Lamport,et al.  Distributed snapshots: determining global states of distributed systems , 1985, TOCS.

[3]  Kees G. W. Goossens,et al.  Transaction-Based Communication-Centric Debug , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[4]  B. Vermeulen,et al.  Core-based scan architecture for silicon debug , 2002, Proceedings. International Test Conference.

[5]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[6]  Wolfgang Fichtner,et al.  Practical design of globally-asynchronous locally-synchronous systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[7]  J. Soden,et al.  The use of light emission in failure analysis of CMOS ICs , 1990 .

[8]  Kees G. W. Goossens,et al.  A high-level debug environment for communication-centric debug , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[9]  Neil Henderson,et al.  Metastability in asynchronous wait-free protocols , 2006, IEEE Transactions on Computers.

[10]  Holger Giese,et al.  Architecture-driven platform independent deterministic replay for distributed hard real-time systems , 2006, ROSATEA '06.

[11]  Josep Torrellas,et al.  CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging , 2006, International Conference on Dependable Systems and Networks (DSN'06).

[12]  Stephen H. Unger,et al.  Hazards, Critical Races, and Metastability , 1995, IEEE Trans. Computers.

[13]  MA Andreas Hansson,et al.  A composable and predictable on-chip interconnect , 2009 .

[14]  Jeremy A. Rowlette,et al.  Critical timing analysis in microprocessors using near-ir laser assisted device alteration (lada) , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[15]  Steve Carr,et al.  A visualization system for multithreaded programming , 2000, SIGCSE '00.

[16]  Santanu Dutta,et al.  Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems , 2001, IEEE Des. Test Comput..

[17]  Bil Lewis,et al.  Debugging Backwards in Time , 2003, ArXiv.

[18]  M. F.,et al.  Bibliography , 1985, Experimental Gerontology.

[19]  Kees G. W. Goossens,et al.  Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[20]  J. Torrellas,et al.  Empowering Software Debugging Through Architectural Support for Program Rollback , 2005 .

[21]  Pia Sanda,et al.  The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA) , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[22]  Kees G. W. Goossens,et al.  A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification , 2005, Design, Automation and Test in Europe.

[23]  Nur A. Touba,et al.  Enhancing Silicon Debug via Periodic Monitoring , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[24]  Kees G. W. Goossens,et al.  Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective , 2006, 2006 International Symposium on Industrial Embedded Systems.

[25]  Wayne P. Burleson,et al.  Synchro-tokens: a deterministic GALS methodology for chip-level debug and test , 2005, IEEE Transactions on Computers.

[26]  R. Leatherman,et al.  An embedding debugging architecture for SOCs , 2005, IEEE Potentials.

[27]  Mario Paniccia,et al.  Novel optical probing technique for flip chip packaged microprocessors , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[28]  Kees G. W. Goossens,et al.  Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[29]  Peter Dahlgren,et al.  Latch divergency in microprocessor failure analysis , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[30]  Romain Desplats,et al.  Fault localization using time resolved photon emission and stil waveforms , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[31]  J. Isoaho,et al.  Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV: Evolutin, Analysis and Trends , 2005 .

[32]  Ieee Standard Test Access Port and Boundary-scan Architecture Ieee-sa Standards Board , 2001 .

[33]  Yu-Chin Hsu,et al.  Visibility enhancement for silicon debug , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[34]  Bart Vermeulen,et al.  Silicon debug of a co-processor array for video applications , 2000, Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786).

[35]  Koen De Bosschere,et al.  RecPlay: a fully integrated practical record/replay system , 1999, TOCS.

[36]  Bart Kienhuis,et al.  Design space exploration of stream-based dataflow architectures: methods and tools , 1999 .

[37]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[38]  Timothy L. Harris.  Dependable software needs pervasive debugging , 2002, EW 10.

[39]  Brian Randell,et al.  Dependability and its threats - A taxonomy , 2004, IFIP Congress Topical Sessions.

[40]  Kees G. W. Goossens,et al.  A Monitoring-Aware Network-on-Chip Design Flow , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[41]  Marc Eisenstadt,et al.  My hairiest bug war stories , 1997, CACM.

[42]  Qiang Xu,et al.  In-band Cross-Trigger Event Transmission for Transaction-Based Debug , 2008, 2008 Design, Automation and Test in Europe.

[43]  Sandeep Kumar Goel,et al.  Automatic generation of breakpoint hardware for silicon debug , 2004, Proceedings. 41st Design Automation Conference, 2004..

[44]  Hendrikus J. M. Veendrick,et al.  The behaviour of flip-flops used as synchronizers and prediction of their failure rate , 1980 .

[45]  Hermann Kopetz,et al.  The fault-hypothesis for the time-triggered architecture , 2004, IFIP Congress Topical Sessions.

[46]  Bart Vermeulen,et al.  Integration of Hardware Assertions in Systems-on-Chip , 2008, 2008 IEEE International Test Conference.

[47]  Wei Liu,et al.  iWatcher: efficient architectural support for software debugging , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[48]  Jim Gray,et al.  Why Do Computers Stop and What Can Be Done About It? , 1986, Symposium on Reliability in Distributed Software and Database Systems.

[49]  Brecht Vermeulen,et al.  Debugging multi-core systems-on-chip , 2010 .

[50]  Thomas J. LeBlanc,et al.  Debugging Parallel Programs with Instant Replay , 1987, IEEE Transactions on Computers.

[51]  Hong Hao,et al.  Clock controller design in SuperSPARC II microprocessor , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[52]  Kees Goossens,et al.  A Network-on-Chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs , 2009, 2009 International Symposium on VLSI Design, Automation and Test.

[53]  Don Douglas Josephson,et al.  Debug methodology for the McKinley processor , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[54]  Rok Sosic,et al.  Relative Debugging Using Multiple Program Versions , 1995 .