An interconnect scheme for reducing the number of contact pads on process control chips

An approach is presented to reduce the number of pads required by electrical test structures by using a multiplexed interconnect scheme. This passive multiplexed scheme requires only two levels of interconnect and can be used for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks. The basic measurement procedure to access individual components is to force a voltage on one of the access pads and then ground one of the group terminals via an ammeter. While an even number of pads is not mandatory it is recommended since this maximizes the efficiency of pad usage. >

[1]  Anthony J. Walton,et al.  Digital measurement of polysilicon to diffusion misalignment for a silicon gate MOS process , 1984 .

[2]  A.J. Walton,et al.  A Novel Approach for an Electrical Vernier to Measure Mask Misalignment , 1989, ESSDERC '89: 19th European Solid State Device Research Conference.

[3]  K. Harada,et al.  Integrated electrical vernier to measure registration accuracy , 1986, IEEE Electron Device Letters.

[4]  A. C. Ipri,et al.  Integrated circuit process and design rule evaluation techniques , 1977 .

[5]  D Vard,et al.  The Measurement of Transistor Characteristics Using On-chip Switching for the Connection of Instrumentation , 1987, ESSDERC '87: 17th European Solid State Device Research Conference.

[6]  H. Sayah,et al.  Linewidth and step resistance distribution measurements using an addressable array , 1990, International Conference on Microelectronic Test Structures.

[7]  J. Trager,et al.  Self-heating and Temperature Measurement in Sub-μm-MOSFETs , 1989, ESSDERC '89: 19th European Solid State Device Research Conference.

[8]  J.T.M. Stevenson,et al.  An Objective Method Of Assessing Metal Patterning Quality , 1988, Proceedings of the IEEE International Conference on Microelectronic Test Structures.

[9]  Anthony J. Walton,et al.  Integrated-circuit test structure which uses a vernier to electrically measure mask misalignment , 1983 .

[10]  C. M. Cork.  Off-line photolithographic parameter extraction using electrical test structures , 1989, Proceedings of the 1989 International Conference on Microelectronic Test Structures.

[11]  Anthony J. Walton,et al.  On-chip switching for DC parametric testing , 1985 .

[12]  A. J. Walton,et al.  Wafer Scale Etch Assessment Using Single Layer Test Patterns , 1986 .

[13]  D.S. Perloff.  A four-point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers , 1978, IEEE Journal of Solid-State Circuits.

[14]  M. G. Buehler,et al.  Parameter Extraction from Spaceborne MOSFETs , 1985, IEEE Transactions on Nuclear Science.

[15]  Nasser Zamani,et al.  Chip-level electromigration measurement technique for multi-segmented interconnect test structures , 1989, Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference.

[16]  G. Freeman,et al.  An Electrical Test Structure For Measuring Contact Size , 1988, Proceedings of the IEEE International Conference on Microelectronic Test Structures.

[17]  Loren W Linholm,et al.  The design, testing, and analysis of a comprehensive test pattern for measuring CMOSSOS process performance and control , 1981 .

[18]  K.L.M. van der Klauw,et al.  Self-multiplexing force-sense test structures for (MOS) IC applications , 1990, International Conference on Microelectronic Test Structures.

[19]  M. Howard,et al.  Automatic test structure modification , 1988, Proceedings of the IEEE International Conference on Microelectronic Test Structures.