Automatic Test Program Generation for Out-of-Order Superscalar Processors

This paper presents a high-level automatic test instruction generation (HATIG) technical that allows, for the first time, to test the scheduling unit of an out-of-order super scalar processor. This technique leverages on existing bounded model checking tools in order to generate software-based self-testing programs from a global EFSM model of the processor under test. The experimental results have demonstrated the efficiency of the proposed technique.

[1]  Dimitris Gizopoulos,et al.  Hybrid-SBST Methodology for Efficient Testing of Processor Cores , 2008, IEEE Design & Test of Computers.

[2]  Kwang-Ting Cheng,et al.  Simulation-Based Functional Test Generation for Embedded Processors , 2006, IEEE Transactions on Computers.

[3]  M.K. Ganai,et al.  Accelerating High-level Bounded Model Checking , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[4]  M. Ümit Uyar,et al.  A method enabling feasible conformance test sequence generation for EFSM models , 2004, IEEE Transactions on Computers.

[5]  Srivaths Ravi,et al.  Systematic Software-Based Self-Test for Pipelined Processors , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Dimitris Gizopoulos,et al.  Software-based self-testing of embedded processors , 2005, IEEE Transactions on Computers.

[7]  Ying Zhang,et al.  Software-Based Self-Testing of Processors Using Expanded Instructions , 2010, 2010 19th IEEE Asian Test Symposium.

[8]  Todd M. Austin,et al.  Using introspective software-based testing for post-silicon debug and repair , 2010, Design Automation Conference.

[9]  Chung-Ho Chen,et al.  Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Tulika Mitra,et al.  Generating test programs to cover pipeline interactions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[11]  Jacob A. Abraham,et al.  Automated mapping of pre-computed module-level test sequences to processor instructions , 2005, IEEE International Conference on Test, 2005..

[12]  Jacob A. Abraham,et al.  A novel functional test generation method for processors using commercial ATPG , 1997, Proceedings International Test Conference 1997.

[13]  Sujit Dey,et al.  A scalable software-based self-test methodology for programmable processors , 2003, DAC '03.

[14]  Kwang-Ting Cheng,et al.  Automatic Functional Test Generation Using The Extended Finite State Machine Model , 1993, 30th ACM/IEEE Design Automation Conference.

[15]  Sujit Dey,et al.  Software-based self-testing methodology for processor cores , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Armin Biere,et al.  Bounded Model Checking Using Satisfiability Solving , 2001, Formal Methods Syst. Des..