Stability Enhancing SRAM cell for low power LUT Design

Abstract Field Programmable Gate Array (FPGA) is the most recently used platform for real time applications such as security and multimedia processing. In FPGA mapping, there is some energy overhead due to the usage of programmable interconnects. To mitigate these limitations an energy efficient six input Look Up Table (LUT) is designed using Stability Enhancing Static Random-Access Memory (SESRAM) cell requiring only seven transistors. The proposed SESRAM cell reduces the area, power consumption, energy consumption, delay and increases the read stability, write stability by minimizing the size of read access transistor as 2 ​nm and maximizing the size of write access transistor as 3 ​nm. The proposed SE7T reduces the write ‘0’ delay and write ’1’ delay by 62.5%, 57.14%, 50%, 40%, 25% and 70%, 62.5%, 57.14%, 50%, 40% respectively at 0.4 ​V when compared with previous SRAM designs such as C6T, D2AP8T, LP8T, ST10T and PFC10T. LUT using SE7T reduces the Write ‘0’ power by 93.4%, 68%, 21.21% and Write ‘1’ power by 2%, 50.16%, 10.13% when compared with LUT design using ST10T, D2AP8T and PFC10T.

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