MicroStandards Special Feature: A Comparison of 32-Bit Buses
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A s promised in the October MicroStandards column, I am presenting a comparison of several well-known 32-bit buses in tabular form this month. Because of the danger of reading too much into this table, and the potential for misunderstanding, I will elaborate on many of the issues. If further clarifications are needed, contact me at Holmbury St-Mary, Dorking, Surrey RH5 6NT, England. It is intended that this subject could form an ongoing discussion in IEEE Micro, and user comments and experience are actively solicited to refine the understanding of the relative advantages and disadvantages of these buses, to benefit the readers of IEEE Micro.
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[2] Hubert D. Kirrmann. Events And Interrupts in Tightly Coupled Multiprocessors , 1985, IEEE Micro.
[3] Randy H. Katz,et al. Implementing a cache consistency protocol , 1985, ISCA 1985.
[4] R. V. Balakrishnan. The Proposed IEEE 896 Futurebus - A Solution to the Bus Driving Problem , 1984, IEEE Micro.