Modelling and performance study of finite-buffered blocking multistage interconnection networks supporting natively 2-class priority routing traffic

In this paper, we model, analyze and evaluate the performance of a 2-class priority architecture for finite-buffered multistage interconnection networks (MINs). The MIN operation modelling is based on a state diagram, which includes the possible MIN states, transitions and conditions under which each transition occurs. Equations expressing state and transition probabilities are subsequently given, providing a formal model for evaluating the MIN's performance. The proposed architecture's performance is subsequently analyzed using simulations; operational parameters, including buffer length, MIN size, offered load and ratios of high priority packets which are varied across experiments to gain insight on how each parameter affects the overall MIN performance. The 2-class priority MIN performance is compared against the performance of single priority MINs, detailing the performance gains and losses for packets of different priorities. Performance is assessed by means of the two most commonly used factors, namely packet throughput and packet delay, while a performance indicator combining both individual factors is introduced, computed and discussed. The findings of this study can be used by network and interconnection system designers in order to deliver efficient systems while minimizing the overall cost. The performance evaluation model can also be applied to other network types, providing the necessary data for network designers to select optimal values for network operation parameters.

[1]  G. Jack Lipovski,et al.  Banyan networks for partitioning multiprocessor systems , 1998, ISCA '98.

[2]  Roch Guérin,et al.  Performance study of an input queueing packet switch with two priority classes , 1991, IEEE Trans. Commun..

[3]  Dietmar Tutsch,et al.  MINSimulate - A MULTISTAGE INTERCONNECTION NETWORK SIMULATOR , 2003 .

[4]  Bin Zhou,et al.  A performance comparison of buffering schemes for multistage switches , 1995, Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing.

[5]  John D. Garofalakis,et al.  An Analytical Performance Model for Multistage Interconnection Networks with Blocking , 2008, 6th Annual Communication Networks and Services Research Conference (cnsr 2008).

[6]  L. Ginsberg,et al.  Cisco Systems , 2003 .

[7]  John D. Garofalakis,et al.  An Approximate Analytical Performance Model for Multistage Interconnection Networks with Backpressure Blocking Mechanism , 2010, J. Commun..

[8]  Bill Dewar,et al.  Load Sharing Replicated Buffered Banyan Networks With Priority Traffic , 1995 .

[9]  Hee Yong Youn,et al.  Performance analysis of finite buffered multistage interconnection networks , 1992, Proceedings Supercomputing '92.

[10]  M. Atiquzzaman,et al.  Realistic modelling of blocked packets for accurate performance evaluation of ATM switches , 1999 .

[11]  Günter Hommel,et al.  Generating Systems of Equations for Performance Evaluation of Multistage Interconnection Networks , 2002, J. Parallel Distributed Comput..

[12]  John D. Garofalakis,et al.  Performance estimation of banyan semi layer networks with drop resolution mechanism , 2012, J. Netw. Comput. Appl..

[13]  Janak H. Patel,et al.  Processor-memory interconnections for multiprocessors , 1979, ISCA '79.

[14]  W. Richard Stevens,et al.  TCP/IP Illustrated, Volume 1: The Protocols , 1994 .

[15]  Yih-Chyun Jenq,et al.  Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network , 1983, IEEE J. Sel. Areas Commun..

[16]  Barrett R. Bryant,et al.  Proceedings of the 1997 ACM symposium on Applied Computing, SAC'97, San Jose, CA, USA, February 28 - March 1 , 1997, SAC.

[17]  Erwin P. Rathgeb,et al.  Performance analysis of buffered Banyan networks , 1991, IEEE Trans. Commun..

[18]  Costas Vassilakis,et al.  Performance Analysis of dual priority single-buffered blocking Multistage Interconnection Networks , 2007, International Conference on Networking and Services (ICNS '07).

[19]  Mohammed Atiquzzaman,et al.  Exact model for analysis of shared buffer ATM switches with arbitrary traffic distribution , 2001 .

[20]  Sidnie Feit,et al.  Local Area High Speed Networks , 2000 .

[21]  Sung-Chun Kim,et al.  Hierarchical multistage interconnection network for shared-memory multiprocessor system , 1997, SAC '97.

[22]  Elizabeth Suet Hing Tse.  Switch fabric architecture analysis for a scalable bi-directionally reconfigurable IP router , 2004, J. Syst. Archit..

[23]  David L. Black,et al.  Definition of the Differentiated Services Field (DS Field) in the IPv4 and IPv6 Headers , 1998, RFC.

[24]  G. E. Rizos,et al.  Routing and Performance Evaluation of Dual Priority Delta Networks under Hotspot Environment , 2009, 2009 First International Conference on Advances in Future Internet.

[25]  Leonard Kleinrock,et al.  Performance analysis of finite-buffered multistage interconnection networks with a general traffic pattern , 1991, SIGMETRICS '91.

[26]  Mohammed Atiquzzaman,et al.  Analysis of shared buffer switches under non-uniform traffic pattern and global flow control , 2000, Comput. Networks.

[27]  Euripidis Glavas,et al.  Performance Evaluation of Two-Priority Network Schema for Single-Buffered Delta Networks , 2007, 2007 IEEE 18th International Symposium on Personal, Indoor and Mobile Radio Communications.

[28]  Josep Torrellas,et al.  The performance of the cedar multistage switching network , 1997, Supercomputing '94.