Variable supply voltage testing for analogue CMOS and bipolar circuits

In this paper a test technique based on the application of power supply levels outside the specified operational range is evaluated with respect to the detection of realistic defects. This work is motivated by two problems encountered in the production test environment. First of all, the test development for analogue circuits is mainly specification driven and as such cannot guarantee a certain fault coverage or quality. Secondly, testing the performance of a state-of-the-art analogue circuit may require application of high performance stimuli (e.g. with respect to frequency or Signal-to-Noise Ratio), while the integrity of such signals is difficult to guarantee because of the non-ideal interface. Two analogue circuits, a CMOS and a bipolar device, are used to evaluate this test technique by means of simulations and to verify it as much as possible by means of measurements.

[1]  Melvin A. Breuer,et al.  Diagnosis and Reliable Design of Digital Systems , 1977 .

[2]  J. C. Henderson,et al.  The use of Marginal Voltage Measurements to Detect and Locate Defects in Digital Microcircuits , 1981, 19th International Reliability Physics Symposium.

[3]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[4]  E. A. Amerasekera,et al.  Failure Mechanisms in Semiconductor Devices , 1987 .

[5]  Thomas M. Storey,et al.  STUCK FAULT AND CURRENT TESTING COMPARISON USING CMOS CHIP TEST , 1991, 1991, Proceedings. International Test Conference.

[6]  John Paul Shen,et al.  Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells , 1984, ITC.

[7]  I. W Stanley,et al.  The application of marginal voltage measurements to detect and locate defects in digital microcircuits , 1982 .

[8]  Manoj Sachdev.  Catastrophic defects oriented testability analysis of a class AB amplifier , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[9]  J. P. Teixeira,et al.  Test preparation and fault analysis using a bottom-up methodology , 1989, [1989] Proceedings of the 1st European Test Conference.

[10]  Andrzej J. Strojwas,et al.  VLSI Yield Prediction and Estimation: A Unified Framework , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Edward J. McCluskey,et al.  Very-low-voltage testing for weak CMOS logic ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[12]  E.M.J.G. Bruls.  Reliability aspects of defect analysis , 1993, Proceedings ETC 93 Third European Test Conference.

[13]  Charles F. Hawkins,et al.  THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[14]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.