Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory

This paper deals with a so-called racetrack memory (also commonly known as a domain-wall memory). Novel circuits for implementing the write, the read, and the shift operations of a Perpendicular Magnetic Anisotropic (PMA) based racetrack cell are initially introduced; the proposed circuits are very efficient in terms of numerous figures of merit, such as delay, power dissipation, and power delay product (PDP). These circuits also allow an efficient implementation of array-level operations of a racetrack memory. An extensive simulation-based analysis is also presented; features such as variations and SEU tolerance in the operation of a PMA-based racetrack memory are considered. This analysis shows that a racetrack memory has great potential due to the significant advantages that it offers for non-volatile storage.

[1]  W. Black,et al.  Programmable logic using giant-magnetoresistance and spin-dependent tunneling devices (invited) , 2000 .

[2]  J. Katine,et al.  Current-induced magnetization reversal in nanopillars with perpendicular anisotropy , 2006, INTERMAG 2006 - IEEE International Magnetics Conference.

[3]  D. Nikonov,et al.  Research directions in beyond CMOS computing , 2007 .

[4]  A. Fert,et al.  The emergence of spin electronics in data storage. , 2007, Nature materials.

[5]  C. Rettner,et al.  Current-Controlled Magnetic Domain-Wall Nanowire Shift Register , 2008, Science.

[6]  D. Stewart,et al.  The missing memristor found , 2008, Nature.

[7]  H. Wong,et al.  Monolithic integration of CMOS VLSI and CNT for hybrid nanotechnology applications , 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

[8]  S. Parkin,et al.  Magnetic Domain-Wall Racetrack Memory , 2008, Science.

[9]  M. Nakayama,et al.  Spin transfer switching in TbCoFe∕CoFeB∕MgO∕CoFeB∕TbCoFe magnetic tunnel junctions with perpendicular magnetic anisotropy , 2008 .

[10]  Weisheng Zhao,et al.  High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits , 2009, IEEE Transactions on Magnetics.

[11]  H. Ohno,et al.  A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction. , 2010, Nature materials.

[12]  H. Ohno,et al.  Current-induced domain wall motion in perpendicularly magnetized CoFeB nanowire , 2011 .

[13]  J. Nowak,et al.  Spin torque switching of perpendicular Ta∣CoFeB∣MgO-based magnetic tunnel junctions , 2011 .

[14]  P. Chevalier,et al.  Racetrack memory cell array with integrated magnetic tunnel junction readout , 2011, 2011 International Electron Devices Meeting.

[15]  Weisheng Zhao,et al.  Perpendicular-magnetic-anisotropy CoFeB racetrack memory , 2012 .

[16]  T. Trypiniotis,et al.  Magnetic domain-wall racetrack memory for high density and fast data storage , 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

[17]  Jose Antonio Rubio Sola,et al.  Process variability in sub-16nm bulk CMOS technology , 2012 .

[18]  M. Gajek,et al.  Spin torque switching of 20 nm magnetic tunnel junctions with perpendicular anisotropy , 2012 .

[19]  Yue Zhang,et al.  Ultra-High Density Content Addressable Memory Based on Current Induced Domain Wall Motion in Magnetic Track , 2012, IEEE Transactions on Magnetics.

[20]  Jacques-Olivier Klein,et al.  Magnetic Adder Based on Racetrack Memory , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Swaroop Ghosh.  Design methodologies for high density domain wall memory , 2013, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

[22]  Hao Yu,et al.  An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[23]  Hao Yu,et al.  Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[24]  F. Lombardi,et al.  HSPICE macromodel of a PMA racetrack memory , 2015, 2015 IEEE Nanotechnology Materials and Devices Conference (NMDC).

[25]  G. Huang,et al.  An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices , 2015, IEEE Transactions on Nanotechnology.