A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS

A low-voltage energy-efficient SAR ADC is presented in this paper with four techniques. Arbitrary weight capacitor array tolerates errors to reduce conversion time. To operate under low voltage, DAC common mode level shift and leakage reduction sample switch with a charge pump are proposed. Differential control logic is used to save its digital power. The prototype ADC consumes 170nW at 100KS/s from a 0.35V supply. It achieves an SNDR of 56.3dB at Nyquist rate and its FOM is 3.2fJ/c.-s.

[1]  Eric A. M. Klumperink,et al.  A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[3]  F. Kuttner.  A 1.2V 10b 20MS/S Non-Binary Successive Approximation ADC in 0.13μm CMOS , 2002 .

[4]  F. Kuttner.  A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).