Novel Re-configurable Circuits For Aging Characterization: Connecting Devices to Circuits

Circuit reliability is a significant concern in scaled technologies. Physical aging models derived by DC stress on discrete devices are accurate to an extent, but can be further improved by evaluating the behaviour of simple circuits such as ring oscillators (RO). In this work, we establish correlation between individual device degradation to circuit’s figure of merit (frequency degradation) to refine understanding of the predictive ability of DC models. We further present novel re-configurable circuits that enables different waveform scenarios seen in design to bridge gaps between DC-stressed device aging and complex circuits. Unique features of this work include: (1) Correlating discrete device degradation to circuit performance degradation, (2) development of a novel PMOS/NMOS aging isolator circuit (PNI) which can isolate the aging contribution of a single device type, and (3) development of a state-of-art re-configurable circuit that modulate waveforms to customize the aging contribution from any particular physical mechanism (NBTI, PBTI, N-HCI or P-HCI).

[1]  Ru Huang,et al.  Diagnosing bias runaway in analog/mixed signal circuits , 2014, 2014 IEEE International Reliability Physics Symposium.

[2]  James Tschanz,et al.  Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating , 2017, IEEE Journal of Solid-State Circuits.

[3]  A. Rahman,et al.  Intrinsic transistor reliability improvements from 22nm tri-gate technology , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[4]  S. Ramey,et al.  Transistor reliability variation correlation to threshold voltage , 2015, 2015 IEEE International Reliability Physics Symposium.

[5]  Tanya Nigam,et al.  Fast Wafer-Level Stress-and-Sense Methodology for Characterization of Ring-Oscillator Degradation in Advanced CMOS Technologies , 2015, IEEE Transactions on Electron Devices.

[6]  S. Kumar,et al.  Investigation of speed sensors accuracy for process and aging compensation , 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

[7]  T. Nigam,et al.  Device reliability metric for end-of-life performance optimization based on circuit level assessment , 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

[8]  T. Nigam,et al.  Assessing device reliability margin in scaled CMOS technologies using ring oscillator circuits , 2017, 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).

[9]  S. Mudanai,et al.  22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[10]  Peter R. Kinget,et al.  Recent advances in in-situ and in-field aging monitoring and compensation for integrated circuits: Invited paper , 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

[11]  A. Rahman,et al.  Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).