Design and Optimization of a Barrel Shifter Unit for DSP

Barrel shifter is one of the most important arithmetic units in Digital Signal Processor. This paper presents a design of a DSP (Digital Signal Processor) barrel shifter unit which implements a new interconnection schedule. The design is optimized by the use of modified 2-to-1 mux. Experiment and simulation results show a great improvement on area and power consumption, which has enhanced the performance of the processor effectively. The DSP which applies this shifter design has been successfully taped out using SMIC 0.18μm CMOS technique.