Segmentation method based modeling and analysis of a glass package power distribution network (PDN)

[1]  Joungho Kim,et al.  Modeling and measurement of simultaneous switching noise coupling through signal via transition , 2006, IEEE Transactions on Advanced Packaging.

[2]  Suresh K. Sitaraman,et al.  Study of cracking of thin glass interposers intended for microelectronic packaging substrates , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[3]  Junho Lee,et al.  Interposer Power Distribution Network (PDN) Modeling Using a Segmentation Method for 3-D ICs With TSVs , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[4]  Joungho Kim,et al.  Analysis of Power Distribution Network in glass, silicon interposer and PCB , 2014, 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC).

[5]  Suresh K. Sitaraman,et al.  Prevention of Cracking From RDL Stress and Dicing Defects in Glass Substrates , 2016, IEEE Transactions on Device and Materials Reliability.

[6]  Joungho Kim,et al.  Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation , 2007, 2007 International Conference on Electronic Materials and Packaging.

[7]  Joungho Kim,et al.  Power distribution networks for system-on-package: status and challenges , 2004, IEEE Transactions on Advanced Packaging.

[8]  V. Sukumaran,et al.  Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[9]  Jae Young Choi,et al.  Decoupling Capacitor Placement in Power Delivery Networks Using MFEM , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[10]  Joungho Kim,et al.  Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[11]  Jun Fan,et al.  Equivalent Circuit Model for Power Bus Design in Multi-Layer PCBs With Via Arrays , 2011, IEEE Microwave and Wireless Components Letters.

[12]  A. Ruehli.  Equivalent Circuit Models for Three-Dimensional Multiconductor Systems , 1974 .

[13]  Joungho Kim,et al.  Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module , 2015, 2015 International 3D Systems Integration Conference (3DIC).

[14]  Stanislaw M. Gubanski,et al.  Dielectric mixtures: electrical properties and modeling , 2001 .

[15]  Philip G. Emma,et al.  Is 3D chip technology the next growth engine for performance improvement? , 2008, IBM J. Res. Dev..

[16]  Joungho Kim,et al.  Noise Coupling Effects on CMOS Analog-to-Digital Converter in Magnetic Field Wireless Power Transfer System Using Chip-PCB Comodeling and Simulation , 2015, IEEE Transactions on Electromagnetic Compatibility.

[17]  Joungho Kim,et al.  Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method , 2010, IEEE Transactions on Advanced Packaging.

[18]  Joungho Kim,et al.  Design and Demonstration of Power Delivery Networks With Effective Resonance Suppression in Double-Sided 3-D Glass Interposer Packages , 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[19]  T. Kurihara,et al.  Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring , 2008, 2008 58th Electronic Components and Technology Conference.