Design of a robust and ultra-low-voltage pulse-triggered flip-flop in 28nm UTBB-FDSOI technology

So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operability of an energy-efficient pulsed-FF was validated at ultra-low operating supply voltage. Measurements of delays and correct functionality are performed in 28nm FDSOI technology. Then, the effect of back bias voltage, a key point in FDSOI technology, is studied and it is shown that our pulsed-FF reaches a minimum operating supply voltage of 170mV.

[1]  David Bol,et al.  A robust and energy efficient pulse generator for ultra-wide voltage range operations , 2013, Fifth Asia Symposium on Quality Electronic Design (ASQED 2013).

[2]  Jiun-In Guo,et al.  A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  Massimo Alioto,et al.  General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.