SET Tolerant Dynamic Logic

This paper presents three SET tolerant dynamic logic circuits. The first one uses redundant PMOS transistors in the precharge circuit and dual redundant pull down networks in the evaluation circuit to mitigate SETs effectively. The second one adds two feedback inverters and two PMOS transistors to harden against SET, even in case of two sequential SETs. The third one connects dual redundant pull down networks in series and uses only one feedback inverter and one PMOS transistor to harden against one or two SETs. Simulation and experimental results demonstrate that these proposed schemes can achieve good SET hardening capability.

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