Replacing global wires with an on-chip network: a power analysis

This paper explores the power implications of replacing global chip wires with an on-chip network. The authors optimized the network links by varying repeater spacing, link pipelining, and voltage scaling, to significantly reduce the energy to send a bit across chip. An analytic model of large chip designs with an on-chip two-dimensional mesh network was developed and the power savings possible in a 70 nm process for two different design points: a circuit-switched ASIC or FPGA design, and a dynamic packet-switched tiled architecture were estimated. For circuit-switched networks, achievable power savings are 35-50% for a mesh with 1 mm links. The packet switched designs use multiplexing and signal encoding to reduce the number of link wires required, but the router overhead limits peak wire power savings to around 20% with optimal tile sizes of around 2 mm.

[1]  Simon Yang.  Scaling and Integration of High Performance Interconnects , 1998 .

[2]  Simon W. Moore,et al.  Low-latency virtual-channel routers for on-chip networks , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[3]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[4]  Li-Shiuan Peh,et al.  Leakage power modeling and optimization in interconnection networks , 2003, ISLPED '03.

[5]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[6]  Li-Shiuan Peh,et al.  High-level power analysis for on-chip networks , 2004, CASES '04.

[7]  Sharad Malik,et al.  A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers , 2003, IEEE Micro.

[8]  Dirk Stroobandt,et al.  The interpretation and application of Rent's rule , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[9]  M. Yazdani,et al.  Microprocessor pin predicting , 1997 .

[10]  Pawan Kapur,et al.  Power estimation in global interconnects and its reduction using a novel repeater optimization methodology , 2002, DAC '02.

[11]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[12]  L. Benini,et al.  Analysis of power consumption on switch fabrics in network routers , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[13]  Lei He,et al.  Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion , 2003, ICCAD 2003.

[14]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[15]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[16]  Krste Asanovic,et al.  Power-optimal pipelining in deep submicron technology , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[17]  Niraj K. Jha,et al.  A High-level Interconnect Power Model for Design Space Exploration , 2003, ICCAD.

[18]  K. Banerjee,et al.  Power dissipation issues in interconnect performance optimization for sub-180 nm designs , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[19]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.