Challenges and limitations of NAND flash memory devices based on floating gates

In this paper, the limitations and challenges of NAND flash memory devices based on floating gates are discussed. And, the newly adopted operation algorithms, such as intelligent incremental step pulse erase, various biasing in grouped W/Ls, virtual negative read and data randomization, and their results are exhibited.

[1]  K. Hsieh,et al.  A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device , 2010, 2010 Symposium on VLSI Technology.

[2]  Ranjeet Alexis,et al.  A multilevel-cell 32 Mb flash memory , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[3]  Mark E. Bauer,et al.  A Multilevel-Cell 32Mb Flash Memory Originally published in ISSCC Digest of Technical Papers 1995 , 2000 .

[4]  Dong Wook Lee,et al.  The Operation Algorithm for Improving the Reliability of TLC (Triple Level Cell) NAND Flash Characteristics , 2011, 2011 3rd IEEE International Memory Workshop (IMW).

[5]  Yo-Hwan Koh,et al.  A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[6]  Kinam Kim,et al.  Future Outlook of NAND Flash Technology for 40nm Node and Beyond , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

[7]  Y.M. Lin,et al.  Improvement of Interpoly Dielectric Characteristics by Plasma Nitridation and Oxidation for Future nand Flash Memory , 2008, IEEE Electron Device Letters.

[8]  YunSeung Shin,et al.  Non-volatile memory technologies for beyond 2010 , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[9]  YeonJoo Jeong,et al.  The challenges and limitations on triple level cell geometry and process beyond 20 nm NAND Flash technology , 2010, 2010 IEEE International Memory Workshop.

[10]  Yeong-Taek Lee,et al.  A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories , 2008, IEEE Journal of Solid-State Circuits.