A 1/4 inch IT-CCD with 640 (H)/spl times/480 (V) square pixels is described. In a progressive-scan CCD, the gate area for charge storage during vertical charge transfer decreases to less than half compared with a conventional CCD. The first objective is increased charge handling capability per unit gate area to compensate for the gate area decrease. The second is suppression of narrow and/or short-channel effect that is important in IT-CCD with channel area shrinkage. Two techniques overcome these problems. One is to avoid the decrease of effective channel width due to alignment error in stepper lithography that has a significant influence in a narrow-channel CCD. To this end, pixel design and processing are improved so one mask step for the buried channel determines channel width (regulated by three mask steps in a conventional CCD). The other is improvement of the doping profile.