On the relation between SAT and BDDs for equivalence checking
暂无分享,去创建一个
[1] Sherief Reda,et al. Combinational equivalence checking using Boolean satisfiability and binary decision diagrams , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[2] Robert K. Brayton,et al. Combinational test generation using satisfiability , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] S. Minato. Binary Decision Diagrams and Applications for VLSI CAD , 1995 .
[4] Joao Marques-Silva,et al. Combinational equivalence checking using satisfiability and recursive learning , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).
[5] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[6] Inês Lynce,et al. An Overview of Backtrack Search Satisfiability Algorithms , 2003, Annals of Mathematics and Artificial Intelligence.
[7] Donald W. Loveland,et al. A machine program for theorem-proving , 2011, CACM.
[8] Tracy Larrabee,et al. Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Jerry R. Burch,et al. Tight integration of combinational verification methods , 1998, ICCAD.
[10] Aaas News,et al. Book Reviews , 1893, Buffalo Medical and Surgical Journal.
[11] Panos M. Pardalos,et al. Satisfiability Problem: Theory and Applications , 1997 .
[12] Randal E. Bryant,et al. On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.
[13] F. Brglez,et al. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .
[14] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).