Ge based high performance nanoscale MOSFETs

It is believed that below the 65-nm node the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Examples of novel device structures being investigated are double gate or surround gate MOS and examples of novel materials are high mobility channel materials like strained Si and Ge, high-k gate dielectrics and metal gate electrodes. Heterogeneous integration of these materials on Si with novel device structures may take us to sub-20 nm regime, but will require new fabrication technology solutions that are generally compatible with current and forecasted installed Si manufacturing.

[1]  Howard R. Huff,et al.  From The Lab to The Fab: Transistors to Integrated Circuits , 2003 .

[2]  D. Antoniadis,et al.  On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit? , 2001, IEEE Electron Device Letters.

[3]  A novel, very high performance, sub-20nm depletion-mode double-gate (DMDG) Si/Si/sub x/Ge/sub (1-x)//Si channel PMOSFET , 2003, IEEE International Electron Devices Meeting 2003.

[4]  K. Saraswat,et al.  Low defect ultra-thin fully strained-Ge MOSFET on relaxed Si with high mobility and low band-to-band-tunneling (BTBT) , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[5]  Chi On Chui,et al.  A germanium NMOSFET process integrating metal gate and improved hi-/spl kappa/ dielectrics , 2003, IEEE International Electron Devices Meeting 2003.

[6]  M. Lundstrom,et al.  Essential physics of carrier transport in nanoscale MOSFETs , 2002 .

[7]  H. Kim,et al.  Atomic layer deposition of high-/spl kappa/ dielectric for germanium MOS applications - substrate , 2004, IEEE Electron Device Letters.

[8]  K. Saraswat,et al.  Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si , 2005, IEEE Electron Device Letters.

[9]  M. Lundstrom.  On the mobility versus drain current relation for a nanoscale MOSFET , 2001, IEEE Electron Device Letters.

[10]  C. O. Chui,et al.  Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality , 2004 .

[11]  Qian Wang,et al.  Germanium nanowire field-effect transistors with SiO2 and high-κ HfO2 gate dielectrics , 2003 .

[12]  Mark S. Lundstrom.  Elementary scattering theory of the Si MOSFET , 1997, IEEE Electron Device Letters.

[13]  D. Antoniadis,et al.  Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress , 2001, IEEE Electron Device Letters.

[14]  J. Bardeen,et al.  The transistor, a semi-conductor triode , 1948 .

[15]  R. Schaller,et al.  Technological innovation in the semiconductor industry: A case study of the International Technology Roadmap for Semiconductors (ITRS) , 2001, PICMET '01. Portland International Conference on Management of Engineering and Technology. Proceedings Vol.1: Book of Summaries (IEEE Cat. No.01CH37199).