Semiconductor Devices in Harsh Conditions

This chapter is dedicated to single-event effects on fullydepleted silicon-on-insulator (FDSOI) complementary metal oxide semiconductor (CMOS). Circuits using two technological nodes are simulated against heavy-ion impact effects: 32 nm bulk and 28 nm FDSOI. The simulations were done using technology computer-aided design (TCAD) tools. CONTENTS 3.

[1]  Ricardo Reis,et al.  SET and SEU simulation toolkit for LabVIEW , 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.

[2]  Robert Ecoffet,et al.  In-flight Anomalies on Electronic Devices , 2007 .

[3]  Andrei Vladimirescu,et al.  Bulk and FDSOI Sub-micron CMOS transistors resilience to single-event transients , 2015, 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS).

[4]  F. Wrobel,et al.  Radioactive Nuclei Induced Soft Errors at Ground Level , 2009, IEEE Transactions on Nuclear Science.

[5]  Jean-Claude Boudenot Radiation Space Environment , 2007 .

[6]  D. Munteanu,et al.  Modeling and Simulation of Single-Event Effects in Digital Devices and ICs , 2008, IEEE Transactions on Nuclear Science.

[7]  Riaz Naseer,et al.  A FRAMEWORK FOR SOFT ERROR TOLERANT SRAM DESIGN , 2008 .

[8]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.